AR# 35903: 12.1 EDK, UARTLite - Why do UART errors rates increase with higher baud and lower clock frequencies?
AR# 35903
12.1 EDK, UARTLite - Why do UART errors rates increase with higher baud and lower clock frequencies?
Description
I found that the bit error rate in the returned data is significantly higher when the baud rate exceeds a certain threshold or the clock rate is decreased. What causes this behavior?
Solution
This is explained in the UARTLite data sheet in Note #5 under Table-2:
With a baud rate of 115200, the sample clock is 16 * 115200 = 1.8432 MHz. With the System clock C_SPLB_CLK_FREQ_HZ running at 10 MHz, the integer ratio for driving the sample clock is 5 (rounding of [10/1.8432]). The UART Lite would then divide the System clock by 5 resulting in 2 MHz for the sample clock. The baud rate error is (1.8432 - 2) /1.8432 => -8.5% which is outside the tolerance for most UARTs. The issue is that the higher the baud rate and the lower the C_SPLB_CLK_FREQ_HZ, the greater the error in the generated baud rate of the UART Lite. Specifications for the baud rate error state that, within 5% of the requested rate is considered acceptable.
This behavior also applies to the UART16550 core.
Click on the error_rate.xlsx to download an Excel spreadsheet that will preform the above calculation on inputs, BAUD rate with C_SPLB_CLK_FREQ_HZ and return an error rate.
Note: the Max Baud rate supported on the Uartlite isC_SPLB_CLK_FREQ_HZ / 16