When I import placement in PlanAhead for a Virtex-6 FPGA design, I receive a message that BUFGDLL is an unrecognized primitive.
Why does this happen? How do I work around it?
BUFGDLL is not a supported primitive for Virtex-6 FPGA designs.
This netlist in this case must have been retargeted from a previous architecture.
To eliminate this error, edit your code and netlist to include only supported primitives.