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AR# 35967

12.1 MAP - Global Optimization Infers SRLs Regardless of "shreg_min_size" or "shreg_extract = no"

Description

I set the "shreg_min_size" or "shreg_extract = no" attribute to prevent XST from inferring SRLs. However, if I enable Global Optimization (global_opt = power/speed/area), MAP resynthesizes the design and infers SRLs regardless of "shreg_min_size" or "shreg_extract = no".

How can I resolve this problem?

Solution

The "shreg_min_size" and "shreg_extract = no" are XST attributes and are not passed to MAP. If you use MAP Global Optimization and do not want the tool to infer SRLs, make sure to apply the "KEEP" constraint to the in-between registers.

The following is an example of Verilog code.

(*KEEP = "true"*) reg d1, d2, d3;

always @ (posedge clk)
begin
d1 <= d;
d2 <= d1;
d3 <= d2;
d_out <= d3;
end

This issue has been fixed in ISE Design Suite 13.2.
AR# 35967
Date Created 12/01/2010
Last Updated 10/20/2011
Status Active
Type General Article
Tools
  • ISE Design Suite - 10.1
  • ISE Design Suite - 10.1 sp1
  • ISE Design Suite - 10.1 sp2
  • More
  • ISE Design Suite - 10.1 sp3
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.0
  • ISE Design Suite - 13.1
  • Less