To quickly determine if a board level reset might be related to this issue, probe the CK clock going to the memory on the board. If the clock is toggling, the configuration is not affected by this issue.
Xilinx has determined the root cause of this issue and is currently putting together an ISE software and MIG rtl fix.
Root Cause - The asynchronous nature of the reset can lead to the BUFPLL_MCB entering an undefined state when used in its current software configuration.
Resolution - To resolve this issue, updated ISE software includes a new BUFPLL_MCB model with additional pins. New MIG/MPMC design files connect the additional pins appropriately to ensure that the BUFPLL_MCB always resets correctly. Thishas beenresolved in ISE tools 12.2/MIG 3.5.
If additional help is required, please open a Web case.
To see a list of other recent and important MCB Answer Records, refer to:
(Xilinx Answer 33566) Design Advisories for MIG including DDR3, DDR2, DDR, Spartan-6 FPGA MCB,RLDRAMII, QDRII+, QDRII, DDRII cores
(Xilinx Answer 34587) MIG v3.4 - Release Notes and Known Issues for ISE Design Suite 12.1
(Xilinx Answer 34609) 12.x EDK - Master Answer Record List
NOTE: If you received the following error message in ISE software 12.2 or higher, see (Xilinx Answer 41985):
ERROR:PhysDesignRules:2268 - Invalid configuration (incorrect pin connections and/or modes) on block:<hierarchy/memcx_infrastructure_inst/BUFPLL_MCB_INST>:<BUFPLL_MCB_BUFPLL_MCB>. In order to ensure proper reset behavior, the GCLK, LOCKED and LOCK pins all need to be connected appropriately. Please see AR#35976 for specific details.