We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

# AR# 35979

## Description

The datasheet does not specify the VP/VN and SM[15:0] input sample current when the ADC is running and performing a conversion.

What is the pin input current when the ADC is running?

## Solution

There isnocurrent specification. What is required is to understandif there is sufficient time forthe high impedance signal to be acquired. If you look at Figure 18 of the Virtex-6 FPGA System Monitor User Guide (UG370), you can see the Equivalent Analog-Input Circuits.

Acquisition time calculations are covered in the "Analog Inputs Description" section of the user guide. There is sufficient information here to be able to calculate what resistance is being used.

tACQ = 7.62 * RMUX * CSAMPLE
tACQ = 4 * ADCCLK (default) or 10 * ADCCLK (if increased acq time is enabled) at ADCCLK max tACQ = 1.92 s

For example,
1.92 s = 7.62 * Reff * 3pF
Reff = 84k ohm

So, if Rmux is 60k ohm for the auxillary inputs (its 200 ohm for VP/VN), the resistor network would be seen in series with the Rmux, and24k ohm would be the maximum resistance of the input. You can reduce the ADCCLK frequency to have a longer tACQ and a bigger input resistance.

You need to make sure that you do not starve the inputs of current but there is nota specification, you need a longer enough ACQ time.

References Virtex-6 FPGA System Monitor User Guide (UG370):
http://www.xilinx.com/support/documentation/user_guides/ug370.pdf

AR# 35979
Date 12/15/2012
Status Active
Type General Article
Devices
• Virtex-6 CXT
• Virtex-6 HXT
• Virtex-6 LX
• More
• Virtex-6 LXT
• Virtex-6 SXT
• Less
Page Bookmarked