We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 35980

SPI-4.2 v9.3 - "ERROR:Pack:1653 At least one timing constraint is impossible to meet..."


If the SPI-4.2 v9.3 Core for Virtex-6 FPGA is used in ISE software 12.1 or later, an error similar to the following might occur:

"ERROR:Pack:1653 At least one timing constraint is impossible to meet because component delays alone exceed the constraint."

The failing paths in the timing report look similar to the following:

Slack: -0.571ns (requirement - (data path - clock path skew + uncertainty))
Source: pl4_v9_3_pl4_snk_top0/U0/io0/DynamicAlign2.dpa2/dpa_top0/LDATA_V6.LDATA[8].DATAPAIR/MASTER_DELAY (OTHER)
Destination: pl4_v9_3_pl4_snk_top0/U0/io0/DynamicAlign2.dpa2/dpa_top0/LDATA_V6.LDATA[8].DATAPAIR/MASTER (FF)
Requirement: 1.250ns
Data Path Delay: 1.601ns (Levels of Logic = 0)(Component delays alone exceeds constraint)
Clock Path Skew: -0.005ns (0.087 - 0.092)
Source Clock: rdclk_div_user rising at 0.000ns
Destination Clock: rdclk0_user falling at 1.250ns
Clock Uncertainty: 0.215ns

Clock Uncertainty: 0.215ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.070ns
Discrete Jitter (DJ): 0.177ns
Phase Error (PE): 0.120ns

Maximum Data Path at Slow Process Corner: pl4_v9_3_pl4_snk_top0/U0/io0/DynamicAlign2.dpa2/dpa_top0/LDATA_V6.LDATA[8].DATAPAIR/MASTER_DELAY to pl4_v9_3_pl4_snk_top0/U0/io0/DynamicAlign2.dpa2/dpa_top0/LDATA_V6.LDATA[8].DATAPAIR/MASTER
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
IODELAYE1.DATAOUT Tiodcko_DATAOUT 1.470 pl4_v9_3_pl4_snk_top0/U0/io0/DynamicAlign2.dpa2/dpa_top0/LDATA_V6.LDATA[8].DATAPAIR/MASTER_DELAY
ISERDESE1.DDLY net (fanout=1) e 0.000 pl4_v9_3_pl4_snk_top0/U0/io0/DynamicAlign2.dpa2/dpa_top0/LDATA_V6.LDATA[8].DATAPAIR/I_p_delay
ISERDESE1.CLKB Tisdck_DDLY_DDR 0.131 pl4_v9_3_pl4_snk_top0/U0/io0/DynamicAlign2.dpa2/dpa_top0/LDATA_V6.LDATA[8].DATAPAIR/MASTER
------------------------------------------------- ---------------------------
Total 1.601ns (1.601ns logic, 0.000ns route)
(100.0% logic, 0.0% route)



To work around the issue, generate and use v10.1 of the SPI-4.2 Core or later. The SPI-4.2v9.3 and earlier are "pre-production" for Virtex-6 FPGA and should not be used in production designs.
AR# 35980
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • SPI-4 Phase 2 Interface Solutions
Page Bookmarked