We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36048

Virtex-6 FPGA Integrated Block for PCI Express - Cannot generate x8 Gen 2 for the XC6VLX365T-3 Part


When targeting a XC64VLX365T-3 device, the customization GUI does not allow you to select a x8 Gen 2 design option.


This is due to a mistake in the tcl file that controls the GUI customization options. The easiest way to fix this is to download a new tcl file found at:

Place this file in the directory:
[XILINX Install Path]/ISE/coregen/ip/xilinx/network/com/xilinx/ip/v6_pcie_v1_5/gui/

Overwrite the existing v6_pcie_v1_5.tcl file and this enables you to generate a x8 Gen 2 design when targeting the XC6VLX365-3 part.

Revision History
06/04/2010 - Initial Release

Linked Answer Records

Master Answer Records

AR# 36048
Date 05/20/2012
Status Archive
Type Known Issues
  • Virtex-6 LXT
  • ISE Design Suite - 12.1
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
Page Bookmarked