AR# 36049

Design Assistant for PCI Express - TRN User Application Interface Questions

Description

This answer record is the starting point for questions regarding the TRN interface for Xilinx cores for PCI Express.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.

Solution

See (Xilinx Answer 36075) regarding packet straddling on the Virtex-6 x8 Gen 2 TRN interface.
See (Xilinx Answer 37042) regarding if the Virtex-6 x8 Gen 2 TRN interface is still used when the core trains to Gen 1 speed.
See (Xilinx Answer 38542) regarding latency through the TRN interface.
See (Xilinx Answer 38552) regarding reasons why trn_tdst_rdy_n may deassert indefinitely.
See (Xilinx Answer 38661) regardingdeassertion of trn_tdst_rdy_n before accepting a complete TLP in V5 PCIe Block Plus core.
See (Xilinx Answer 34260) regarding why trn_terr_drop_n may assert?

Revision History
07/30/2011 - Added 38542, 38552, 38661, 34260.
08/13/2010 - Initial Release

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Linked Answer Records

Child Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
38661	Design Assistant for PCI Express - Endpoint Block Plus - Can trn_tdst_rdy_n deassert during the middle of a packet being transmitted on the TRN interface?	N/A	N/A
34260	Design Assistant for PCI Express - trn_terr_drop_n Asserted when Transmitting a Valid Packet	N/A	N/A

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
38552	Design Assistant for PCI Express - Reasons for trn_tdst_rdy_n Deasserting Indefinitely	N/A	N/A
37042	Design Assistant for PCI Express - Is 128-bit interface maintained when x8 Gen2 comes up in Gen1 speed?	N/A	N/A
36075	Design Assistant for PCI Express - 128-bit interface with packet straddling	N/A	N/A
38542	Design Assistant for PCI Express - How to Calculate the Latency of a Packet Presented on the TRN Interface	N/A	N/A

AR# 36049
Date	12/15/2012
Status	Active
Type	General Article
Devices	Virtex-6 CXT Virtex-6 HXT Virtex-6 LXT Virtex-6 SXT Spartan-6 LXT Virtex-5 FXT Virtex-5 LXT Virtex-5 SXT Virtex-5 TXT More Less
IP	Virtex-6 FPGA Integrated Block for PCI Express ( PCIe ) Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe ) Endpoint Block Plus Wrapper for PCI Express

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