UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36107

ModelSim - Fatal: (vsim-7) Failed to open VHDL file "./fir_core_init.mif" in rb mode

Description

Running a simulation of a design that instantiates a core containing initialization data (via COE or MIF files) results in the following error:

# Loading xilinxcorelib.fir_compiler_v5_0_mac_fir(behavioral)
# ** Fatal: (vsim-7) Failed to open VHDL file "./dor_ddc_fir_hb2.mif" in rb mode.
# No such file or directory. (errno = ENOENT)


Why does this issue occur and how can it be resolved?

Solution

Core Generator creates memory initialization files (.mif) that contain the memory initialization data specified in coefficient files (.COE) for certain cores (For example the Block Memory Generator and FIR Compiler cores). 

The .mif file is referenced in the simulation wrappers with the expectation that the file will be located in the same location as that of the simulation directory. 

If the cores are generated in a location other than the simulation working directory, the error above will occur.

To resolve this issue, identify the .mif file located in the folder where the cores have been generated and either copy or move the file to the simulation working directory. 

If launching the simulation from ISE, this is the same folder as the folder where the .xise ISE project file resides.


AR# 36107
Date Created 06/09/2010
Last Updated 02/18/2015
Status Active
Type General Article
Tools
  • ISE Design Suite