We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36125

Serial RapidIO - Logic resource utilization in different Flow Control modes


The Xilinx Buffer core in SRIO can support both TX Controlled Flow Control and RX Controlled Flow Control. Which one can save logic resource utilization? If I choose RX Controlled mode, will the TX controlled logic be implemented?


RX flow control uses much less logic compared to TX flow control.

If you select Receiver Controlled Flow Control in the CORE Generator tool, then Transmitter flow control logic will not be implemented, thereby saving resources.

However, if you select Transmitter Controlled Flow Control, the core will first attempt to use Transmitter Controlled Flow Control and then it can switch to Receiver Controlled mode if the link partner cannot support Transmitter Controlled Flow Control. Therefore, if Transmitter Controlled Flow Control is selected in Coregen, the Receiver Controlled Flow Control logic will be implemented.
AR# 36125
Date 12/15/2012
Status Active
Type General Article
  • Serial RapidIO
Page Bookmarked