AR# 36139


Spartan-6 - When using the DCM with Dynamic Phase Shift, how long does it take PSDONE to assert?


What is the specification for PSDONE to assert when doing dynamic phase shift in the Spartan-6 DCM?


The timing of the PSDONE asserting in Spartan-6 FPGA is the same as the Spartan-3 FPGA Generation.

The phase adjustment might require as many as 100 CLKIN cycles plus 3 PSCLK cycles to take effect, at which point the DCMs PSDONE output goes High for one PSCLK cycle. In most cases, it will take much less time than this, so it is recommended to monitor PSDONE instead of counting CLKIN clock cycles for determining when the phase shift is complete.
AR# 36139
Date 12/15/2012
Status Active
Type General Article
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