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AR# 36263

12.1 Application Note XAPP 1123 - The lte_duc_cfr System Generator model produces errors. How can I work around it?


For the Application Note XAPP1123, I see a summary of Errors:

Error 0001: Illegal input type on port: a
Block: 'downlink_design/LTE DFE Downlink/DUC Configurable Subsystem/DUC_4x5/gain_ctrl/DSP48 Macro/DSP48'

Error 0001:

Reported by:
'downlink_design/LTE DFE Downlink/DUC Configurable Subsystem/DUC_4x5/gain_ctrl/DSP48 Macro/DSP48'

The a port is being driven by a Fix_30_0.
The a port must be a Fix_18_0.

Error occurred during "Rate and Type Error Checking".

This error is due an illegal signal type being produced from the "downlink_design/LTE_DFE_Downlink/DUC Configurable Subsystem/DUC_4x5/gain_ctrl/DSP48 Macro/xlreinterpretdsp48macro," which then feeds back through the design causing the error described.


To work around the issue:

1. Open the "downlink_design/LTE_DFE_Downlink/DUC Configurable Subsystem/DUC_4x5/gain_ctrl/DSP48 Macro/xlreinterpretdsp48macro,"
2. Check the "Specify explicit sample period" tick box. and click "OK".
3. Then, open the "downlink_design/LTE_DFE_Downlink/DUC Configurable Subsystem/DUC_4x5/gain_ctrl/DSP48 Macro/DSP48" block, and click "OK" to close.
4. Then, in "downlink_design/LTE_DFE_Downlink/DUC Configurable Subsystem/DUC_4x5/gain_ctrl/DSP48 Macro" block, open the block and select "OK" to close.
5. The "downlink_design/LTE_DFE_Downlink/DUC Configurable Subsystem/DUC_4x5/power_meter/DSP48 Macro" needs to be modified in the same manner as described above.
6. Then, save the design and re-run the simulation. Design should successfully simulate.

Note: The design will show some IP are superseded warnings. Good advice would be to look at the CFR and DUC/DDC Compiler IP available in the Coregen IP library for implementation of Digital Front end systems
AR# 36263
Date 01/18/2012
Status Active
Type General Article
  • ISE Design Suite - 12.1
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