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AR# 36277

14.x Timing - Component Switching Limit Checks of DCM output clocks when CLK2X is used for Feedback


I receive the following Component Switching Limit Check errors in the Timing report in an S6 design (-2 speed grade). It says the maximum frequency of CLKIN is 166.945 MHz. While in the S6 DC and Switching Characteristics Datasheet, it says the maximum frequency of CLKIN is 250 MHz. I am using CLK2X output as the Feedback clock of DCM. Why does the CLKIN have a max frequency of 166.945 MHz?

Slack: -2.623ns (period - min period limit)
Period: 3.367ns
Min period limit: 5.990ns (166.945MHz) (Tdcmper_CLKIN)
Physical resource: u_sp6_sdi_top/u_sp6_demo_top/gtp_interface_dcm_rx/CLKIN
Logical resource: u_sp6_sdi_top/u_sp6_demo_top/gtp_interface_dcm_rx/CLKIN
Location pin: DCM_X0Y6.CLKIN
Clock network: u_sp6_sdi_top/u_sp6_demo_top/gtpclkout1_1_bufio
Slack: -2.623ns (period - min period limit)
Period: 3.367ns
Min period limit: 5.990ns (166.945MHz) (Tdcmper_CLKOUT)
Physical resource: u_sp6_sdi_top/u_sp6_demo_top/gtp_interface_dcm_rx/CLK0
Logical resource: u_sp6_sdi_top/u_sp6_demo_top/gtp_interface_dcm_rx/CLK0
Location pin: DCM_X0Y6.CLK0
Clock network: u_sp6_sdi_top/u_sp6_demo_top/rxusrclk_pre
Slack: -2.276ns (period - min period limit)
Period: 6.734ns
Min period limit: 9.010ns (110.988MHz) (Tdcmper_CLKDV)
Physical resource: u_sp6_sdi_top/u_sp6_demo_top/gtp_interface_dcm_rx/CLKDV
Logical resource: u_sp6_sdi_top/u_sp6_demo_top/gtp_interface_dcm_rx/CLKDV
Location pin: DCM_X0Y6.CLKDV
Clock network: u_sp6_sdi_top/u_sp6_demo_top/rxusrclk2_pre


Because the CLK2X output is used as the Feedback clock of DCM, the CLKIN has to meet a half of the maximum frequency requirement of CLK2X, which is (334/2=167) MHz for S6 device (-2 speed grade). So the max frequency of CLK0 is (334/2=167) MHz. And, the maximum frequency of CLKDV is (334/1.5111) MHz.

AR# 36277
Date 12/15/2012
Status Active
Type General Article
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