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AR# 36304

ISE Simulator - Wait Statement not supported within Fork/Join statements in Verilog testbenches

Description

When Fork/Join statements contain Wait statements within Tasks in Verilog Testbenches, the following error types can be reported by ISE simulator.


1) ERROR: In process
FATAL ERROR:ISim: This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To search for possible resolutions to this issue, refer to the Xilinx answer database by going to http://www.xilinx.com/support/answers/index.htm and search with keywords 'ISim' and 'FATAL ERROR'. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.


The Fatal error shown above occurs when there is a nested Fork/Join within a Fork/Join statement and a Wait performed in the task as well.

For example:


task <sample>;
fork
begin
fork
begin
wait (a || b || c);
.....
end
join
end
join

2) ERROR: Hierarchical wait for forked process inside subprogram not supported.


This occurs when onlyone fork/join statement exists.

For example:

task <sample>;
fork
begin
begin
wait (a || b || c);
.....
end
end
join

Solution

This issue is currently under investigation in order to resolve the problem in a future release of the ISE Design Suite software.

To work around the issue, replace fork/join with begin/end statements

For example:

Extract Failing Code:

task do_reset; //wb_b3_ok
fork
begin
reset = 1'b1 ;
#100 ;
@(posedge pci_clock) ;
reset <= 1'b0 ;
@(posedge pci_clock) ;
end
begin:monitor_pci_oes_for_reset_duration
reg error ;

wait(RST === 1'b0) ;

@(posedge pci_clock) ;

fork
begin:monitor_pci_oes

while (RST === 1'b0)
begin
wait( //JoshEdit was an @ also the ||s were ors, and the bridge32_top was `PCI_BRIDGE_INSTANCE
bridge32_top.INTA_en ||
bridge32_top.REQ_en ||
bridge32_top.FRAME_en ||
bridge32_top.IRDY_en ||
bridge32_top.DEVSEL_en ||
bridge32_top.TRDY_en ||
bridge32_top.STOP_en ||
bridge32_top.AD_en ||
bridge32_top.CBE_en ||
bridge32_top.PAR_en ||
bridge32_top.PERR_en ||
bridge32_top.SERR_en
) ;

check_pci_oes_during_reset(error) ;

if (error)
begin
$display("At Time %t", $time) ;
$display("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
end
end
end
begin:wait_reset_end
if (RST === 1'b0)
@(posedge RST) ;

disable monitor_pci_oes ;
end
join

check_pci_oes_during_reset(error) ;

if (error)
begin
$display("At Time %t", $time) ;
$display("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
end
end
join
endtask

Fixed Code extract:

task do_reset; //wb_b3_ok
//fork
begin
begin
reset = 1'b1 ;
#100 ;
@(posedge pci_clock) ;
reset <= 1'b0 ;
@(posedge pci_clock) ;
end
begin:monitor_pci_oes_for_reset_duration
reg error ;

wait(RST === 1'b0) ;

@(posedge pci_clock) ;

// fork
begin:monitor_pci_oes

while (RST === 1'b0)
begin
wait( //JoshEdit was an @ also the ||s were ors, and the bridge32_top was `PCI_BRIDGE_INSTANCE
bridge32_top.INTA_en ||
bridge32_top.REQ_en ||
bridge32_top.FRAME_en ||
bridge32_top.IRDY_en ||
bridge32_top.DEVSEL_en ||
bridge32_top.TRDY_en ||
bridge32_top.STOP_en ||
bridge32_top.AD_en ||
bridge32_top.CBE_en ||
bridge32_top.PAR_en ||
bridge32_top.PERR_en ||
bridge32_top.SERR_en
) ;

check_pci_oes_during_reset(error) ;

if (error)
begin
$display("At Time %t", $time) ;
$display("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
end
end
end
begin:wait_reset_end
if (RST === 1'b0)
@(posedge RST) ;

disable monitor_pci_oes ;
end
// join

check_pci_oes_during_reset(error) ;

if (error)
begin
$display("At Time %t", $time) ;
$display("The PCI Bridge didn't provide expected values on output enable signals during reset") ;
end
end
//join
end
endtask
AR# 36304
Date Created 09/02/2010
Last Updated 12/15/2012
Status Active
Type General Article
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2