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AR# 36322

D.2010.03 Synplify Pro does not insert I/O buffers for the RX and TX pins for GTPs and results in trimming


When instantiating GTP/GTX using Synplify Pro,the TX and RX data pins are trimmedin the final netlist and the following warning message occurs in translate:
" WARNING:ConstraintSystem:119 - Constraint < NET "SFP1_RX_n" LOC = AP6; >
[FPGA_TOP.ucf(1325)]: This constraint cannot be distributed from the design
objects matching 'NET "SFP1_RX_n"' because those design objects do not
contain or drive any instances of the correct type."


This warning occurs because Synplify Pro does not insert IOBUFs on TX and RX data pins. The pads, which do not have IOBUFs, can be found in the Translate report through the above warning messages. This issue is seen in D.2010.03 version of SynplifyPro.
The work-around is to instantiate IBUF and OBUF in the HDL code manually.
The Synplify Development team is actively working on fixing this issue.
AR# 36322
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 CXT
  • Virtex-6 HXT