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AR# 36335

MIG v3.3, v3.4 Virtex-5 DDR2 - Data corruption occurs at the beginning or end of a read burst


In the MIG 3.3 and MIG 3.4 versions of the Virtex-5 DDR2 MIG design, the training pattern used for DQS gate timing calibration is not correct. This can lead (in some cases) to lack of timing margin on the transfer of the DQS gate control signal from the CLK0 to the DQS clock domain. This lack of timing margin can cause the DQS gate to be enabled and/or disabled one cycle too early or too late causing data corruption at the beginning or end of a read burst (or series of read bursts, if they occur back-to-back).

The occurrence of these cases is a function of the starting phase between the DQS and a signal drive in the DQS gate generation logic driven by the BUFG clock, and can vary between particular devices and memories. It is strongly recommended that customers using MIG 3.3 and MIG 3.4-based Virtex-5 DDR2 MIG designs follow the workaround provided in this answer record. Designs outside of MIG 3.3 and MIG 3.4 do not have this issue. The issue will be resolved in MIG 3.5.

For detailed information on the Virtex-5 DDR2 design scheme, please see XAPP858.


To work around this issue, download the below zip file and replace the included ddr2_phy_write.v/.vhd file located in the generated 'rtl' directory:

AR# 36335
Date 12/15/2012
Status Active
Type General Article
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • More
  • Virtex-5 SXT
  • Virtex-5 TXT
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  • MIG