AR# 36347


12.1 EDK - I/O Buffers are inserted when using a EDK design as a sub-module in an ISE project


I have instantiated an EDK design as a sub-module in the ISE software.

There are I/O Buffers automatically inserted on the ports from the EDK design and as a result it is failing synthesis.

What is the cause of this problem?


By default, XST would not insert IOBs if the EDK design is a sub-system.

However, if it is a bi-directional I/O, XST will insert IOB's.

Taking GPIO as an example, when GPIO_IO is used, an I/O Buffer is inserted by PlatGen automatically.

If you need to connect the GPIO port to other logic in the ISE design, the GPIO_IO_I, GPIO_IO_O and GPIO_IO_T ports should be used.

There are also a small number of cores that have IOB instantiated inside of HDL code, such as MPMC.

These cores are supposed to be connected to external devices directly and should not be used for internal logic.
AR# 36347
Date 10/02/2014
Status Active
Type General Article
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