Version Found: 1.1; v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45702).
The Spartan-6 FPGA Endpoint Block for PCI Express User Guides (UG564 and UG672) state that the starting addresses of the optional user-implemented configuration space registers are customizable.
However, there is no way to customize it in the CORE Generator GUI.
How do I implement these user space registers?
These starting addresses are not customizable; they are hardcoded values.
If you enable the optional configuration space registers, the starting and ending addresses are as follows:
Once enabled, you must respond to any configuration access within these ranges.
If not implemented, you must respond with a successful completion with data of 0x00000000.
Additionally, to enable the PCIe extended range, the DSN capability must be enabled.
01/18/2012 - Updated; added reference to (Xilinx Answer 45702)
07/06/2011 - Updated for 2.3 release
12/24/2010 - Updated for 2.2 release
10/05/2010 - Initial Release
NOTE: "Version Found" refers to the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.