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AR# 36456

Block Memory generator v4.2 - Release Notes and Known Issues for ISE 12.2

Description

This Release Notes and Known Issues Answer Record is for the Block Memory Generator v4.2 Core, released in ISE 12.2, and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues-
- Technical Support

Solution

General Information

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

For the most recent updates to the IP installation instructions for this core, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm

For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm

This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v4.2 solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm

New Features in v4.2

- ISE 12.2 support
- Soft-ECC support for Virtex-6 and Spartan-6 devices

Resolved Issues in v4.2

1.Virtex-6 BRAM Memory collision error

- When the user selects SDP - in Virtex-6 devices
Solution: For SDP configuration, the write_mode is set as Read_First when Common Clock is enabled otherwise the write_mode is set as Write_First
- CR 564035

2. Memory leak in BMG causes other applications to fail

Solution: Memory leak due to BMG is considerably reduced after deleting redundant memory
- CR 557149

Known Issues in v4.2

The following are known issues for v4.2 of this core at time of release:

Additional Memory Collision Restrictions: Address Space Overlap

- Virtex-6 BRAM Memory collision error

1. When the user selects TDP (write_mode= Read First)
Impact: User will have to consider collision Issue

- Spartan-6 BRAM Memory collision error

1. When the user selects TDP (write_mode= Read First)
Impact: User will have to consider collision Issue
Note: Refer to UG383, 'Conflict Avoidance' section while using TDP Memory, with
Write Mode = Read First in conjunction with asynchronous clocking

2. When the user selects SDP ? Fixed Primitives ? 256 x 36:
- Internally, the core will use 512 x 36 primitives.
-The memory utilization may double based on the user depth x width selection.

3. When the user selects SDP ? Minimum Area or Low Power algorithm:
- Internally, the core will use 512 x 36 primitives instead of 256 x 36 primitives.
- The memory utilization may double based on the user depth x width selection.

Technical Support

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product. Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation, and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.
AR# 36456
Date Created 06/29/2010
Last Updated 07/29/2010
Status Active
Type Known Issues