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AR# 36505

MIG 7 Series and Virtex-6 DDR2/DDR3 Solution Center Design Assistant - Bank Machines


Bank machines are the main logic block within the memory controller. 

When a request (single Write/Read) is accepted, it is assigned to a bank machine. 

The bank machine is then responsible for issuing all commands necessary to complete the request.

  • Generate Row and Column commands adhering to DRAM timing requirements.
  • Column commands may be reordered to optimize throughput.

Once the request is completed, the bank machine is released and made available for assignment to another request.

The Bank Machines correspond to a given DRAM bank at a given time (while a request is assigned). 

The assignment of Bank Machines is dynamic. 

There is not a need to have a Bank Machine for each physical DRAM bank.

Note: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) 

The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Bank Machine Usage

By default, the MIG output uses four Bank Machines. The design allows between two to eight Bank Machines where the trade-off is area versus performance. 

Increasing the number of Bank Machines might improve the overall efficiency of the memory controller. 

Behavioral simulation with the desired address/traffic pattern should be run to determine efficiency changes. 

The number of Bank Machines is configured through RTL parameters in the memc_ui_top.v/.vhd module.

  • BM_CNT_WIDTH* = The width required for the Bank Machine counter. If four bank machines are used, BM_CNT_WIDTH needs to be set to two. If eight Bank Machines are used, BM_CNT_WIDTH needs to be set to three.
  • nBANK_MACHS** = The number of Bank Machines. This is set to four by default, but can be changed to a value between two and eight. When changing the number of Bank Machines, simulate the target traffic pattern to see a change in performance. Also, ensure timing is met.

*BM_CNT_WIDTH is only included in the Virtex-6 FPGA designs.

** As this number is increased, FPGA logic timing becomes more challenging and timing failures may occur depending on design and memory configuration.

For 7 Series Vivado designs, out-of-context (OOC) flow cannot be used.  Use a non-OOC flow to manually modify the parameter.

For EDK users, a custom pcore should be created whenever parameter changes are made. 

The following instructions can be followed to modify the bank machine parameters:

1. Open XPS project of the design.
2. In the system assembly view of the XPS GUI, right click on axi_7series_ddrx (DDR3_SDRAM) IP and select option Make This IP Local.
3. Navigate to local pcore directory of the XPS project.
4. Locate BM_CNT_WIDTH and nBANK_MACHS parameters inside  "../sources_1/edk/MicroBlaze_ProcessorSubSystem/pcores/axi_7series_ddrx_v1_08_a/hdl/verilog/<core_name>_mig.v" module:
5. Generate the bitstream again with this rtl change.

Additional Information

  • See the Virtex-6 FPGA Memory Interface Solutions User Guide (UG406) under Core Architecture > Memory Controller > Bank Machines:
  • See the 7 Series FPGA Memory Interface Solutions User Guide (UG586) under Core Architecture > Memory Controller > Bank Machines: 
  • (Xilinx Answer 34942) Reordering Logic.
  • (Xilinx Answer 35410) How many commands can be stored?
  • (Xilinx Answer 34392) Controller Efficiency
  • (Xilinx Answer 36883) Can multiple banks be open at the same time? If so, how many?

Revision History
05/01/2014 - Updated EDK and timing information

09/19/2012 - Minor Updates
08/24/2010 - Added link to 36883

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Associated Answer Records

AR# 36505
Date 06/27/2014
Status Active
Type Solution Center
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Less
  • MIG
  • MIG 7 Series
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