We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36508

MIG 7 Series and Virtex-6 MIG DDR2/DDR3 Solution Center Design Assistant - Column Machines


A Column Machine is responsible for generating timing information necessary to manage the DQ data bus. Because there is only one DQ bus, each MIG design has only one Column Machine. The Column Machine monitors the commands issued by the Bank Machines and generates inhibit signals to ensure the DQ bus is utilized properly.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


For additional information on Column Machines, refer to UG586 and UG406 under Core Architecture > Memory Controller > Column Machines.

Linked Answer Records

Master Answer Records

AR# 36508
Date 05/26/2014
Status Archive
Type Solution Center
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Less
  • MIG
  • MIG 7 Series
Page Bookmarked