We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36509

MIG 7 Series and Virtex-6 MIG DDR2/DDR3 Solution Center Design Assistant - Arbitration Block


The 7 Series and Virtex-6 DDR2/DDR3 MIG Memory Controller includes an Arbitration Block. The purpose of this block is to receive requests from the Bank Machines to send commands to the DRAM array. For each command, the block selects a row and column command to forward to the physical layer. The Arbitration Block implements a round robing protocol to ensure forward progress.

NOTE: This answer record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Additional Information

  • See UG586 or UG406 under Core Architecture > Memory Controller > Arbitration Block for more information.
  • For information on Bank Machines, see (Xilinx Answer 36505)

Linked Answer Records

Master Answer Records

AR# 36509
Date 09/18/2012
Status Active
Type Solution Center
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-7
  • Kintex-7
  • Artix-7
  • Less
  • MIG
  • MIG 7 Series
Page Bookmarked