We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36550

MIG v3.5, Spartan-6 MCB - Synplify fails on a MIG output design with error "port LOCKED does not exist"


When I synthesize a MIG Spartan-6 FPGA MCB design using Synplify Pro, errors similar to the following occur:

@E: CS168 :"/example_design/rtl/memc3_infrastructure.v":284:18:284:18|port LOCKED does not exist 
@E: CS168 :"/example_design/rtl/memc3_infrastructure.v":284:18:284:18|Illegal or Unsupported Syntax within black box. Use: // synthesis  translate_off { unsupported Verilog } // synthesis translate_on

Why do these errors occur and how do I resolve them?


This issue occurs due to a pin update in the BUFPLL_MCB primitive for Spartan-6 FPGA.

MIG supports Synplicity D-2009.12, however, the Synplify tools have not yet been updated to include the revised BUFPLL_MCB primitive.

For details on the primitive change, see (Xilinx Answer 35976).


Synplicity has created an updated BUFPLL_MCB model that can be downloaded from their support website. 

For instructions on using the updated model and a link to the model, please visit the following Solvnet Article: https://solvnet.synopsys.com/retrieve/030979.html?otSearchResultSrc=advSearch&otSearchResultNumber=1&otPageNum=1


The Xilinx provided unisim BUFPLL_MCB model can be used if it is treated as a black box. 

This is an alternative work around to Option 1.
  1. Copy the BUFPLL_MCB.v file from $XILINX/verilog/src/unisims/BUFPLL_MCB.v and paste it in the MIG output "par" directory.
  2. Update the model to add syn_black_box and translate_off/on constructs.
    This is shown in the BUFPLL_MCB.v file attached to this answer record (see link below).
  3. Update the script_synp.tcl file to compile the BUFPLL_MCB.v model: add_file -verilog "../par/BUFPLL_MCB.v"
    The updated script_synp.tcl is also attached for reference.
  4. Execute the "ise_flow.sh" script (or "ise_flow.bat" in case of Windows) in the par directory.
    This work-around will allow Synplify to synthesize the updated model. Similar steps can be followed for VHDL designs.
ZIP file with example files:

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
36211 MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
39128 MIG Virtex-6 and Spartan-6 v3.7 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
AR# 36550
Date 09/03/2014
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • MIG
Page Bookmarked