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AR# 36554

MIG v3.5 Virtex-6 Multi-Controller Designs - Failure occurs in MAP when controllers require separate REFCLK frequencies (200 and 300 MHz)


The Virtex-6 FPGA MIG design uses a REFCLK of 300 MHz for designs running above 480 MHz and a REFCLK of 200 MHz for designs running below 480 MHz.

Consequently, it is possible for a MIG multi-controller output to have REFCLKs running at both 200 MHz and 300 MHz. 

When this combination occurs, MAP incorrectly fails with the following message:

ERROR:PhysDesignRules:1613 - IDELAYCTRL not found for clock region CLOCKREGION_X0Y8. The IODELAYE1 block c0_u_memc_ui_top/
gen_loop_col0.u_odelay_rsync has an IDELAY_TYPE attribute of either FIXED or VARIABLE. This programming requires that there be an IDELAYCTRL block programmed within the same clock region.

More IDELAYCTRL resources are used in this scenario than are required.

This results in the following message in the MAP report file (*.mrp):

Number of IDELAYCTRLs: 72 out of 36 200% (OVERMAPPED)

This failure occurs in the following scenarios:

  • DDR3 multi-controller designs where one controller frequency is 480 MHz and above and another controller frequency is below 480 MHz. 

  • Multi-Controller design with a DDR3 controller frequency above 480 MHz and a QDRII+ controller.

No failures occur for single controller designs and multi-controller designs containing only QDRII+.

The underlying reason for the failure is that the ISE software is not able to replicate IDELAYCTRLs for locked IODELAYs that do not have connectivity with IOBs (IODELAY-BUFIO and IODELAY-OLOGIC groups).

This issue is scheduled to be resolved in the ISE 12.3 implementation tools.

Until these tools are available, this Answer Record details the required work-around.


This issue is resolved in ISE12.3.


To work around this issue , modifications to both MIG generated RTL files and the UCF are required.

RTL Changes: (applies to both Verilog and VHDL designs)

  1. iodelay_ctrl module (located in 'rtl/ip_top' directory): By default, MIG provides one IDELAYCTRL instance with the IODELAY_GROUP attribute. This instructs the tools to replicate IDELAYCTRLs as required. Since this replication is not working for this case, IDELAYCTRL instances must be manually provided for each I/O column, and the instances cannot contain the IODELAY_GROUP attribute. Modified iodelay_ctrl module for both Verilog and VHDL are attached (see link below).These files are provided for reference only. Manual modification in your design is required.
  2. phy_rdclk_gen module (located in 'rtl/phy' directory): IODELAY_GROUP attribute need to be removed from the IODELAYE1 primitives for all u_odelay_rsync instances. Modified phy_rdclk_gen module of both Verilog and VHDL versions are attached (see the link below) to serve as an example.
  3. example_top module (located in 'rtl/ip_top' directory): RTL parameters (nDQS_COL0, nDQS_COL1, nDQS_COL2 and nDQS_COL3) need to be declared in the iodelay_ctrl module component declaration and should be mapped properly in the iodelay_ctrl module instances. nDQS_COL parameter values should, in the iodelay_ctrl module, be mapped to the proper controller nDQS_COL parameters. These parameters should map using the same controller number of the TCQ parameter. For example, if TCQ is C2_TCQ in the iodelay_ctrl port map, then the nDQS_COL should be mapped to C2_nDQS_COL.

UCF Changes:
  • IDELAYCTRL LOC constraints need to be provided for the IODELAYE1 primitives of the BUFR constraints. MIG generates the LOC constraints for the IODELAYE1 primitives. One IDELAYCTRL is required per clock region (clock region = bank). BUFR constraints are provided for each I/O column containing Data Groups for each controller. Therefore, IDELAYCTRL constraints must be provided in the UCF for each BUFR based on the number of I/O columns selected for Data Group (for example, if Data Groups span two I/O columns, two BUFR constraints will exist and two IDELAYCTRL constraints must be manually provided). The user needs to calculate the IDELAYCTRL LOC value based on BUFR IODELAYE1 constraints and provide the constraints in the UCF file.
NOTE: It is possible to leave one IDELAYCTRL group unconstrained and have the tools properly LOC the site.

IDELAYCTRL LOC calculation:
IDELAYCTRL LOC value can be calculated based on the u_odelay_rsync LOC constraints provided in the UCF. In u_odelay_rsync LOC constraint, X location should be taken as is for IDELAYCTRL LOC and the Y location value is equal to the Y location value of the u_odelay_rsync LOC constraint divided by 40 (rounded down). For example, if the u_odelay_rsync LOC constraints is IODELAY_X2Y181, the IDELACYCTRL constraint value is IDELAYCTRL_X2Y4.

Example -If MIG generates the BUFR constraints as follows:
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col0.u_odelay_rsync"
INST "c0_u_memc_ui_top/u_mem_intfc/phy_top0/u_phy_read/u_phy_rdclk_gen/gen_loop_col1.u_odelay_rsync"

The IDELAYCTRL constraints should be provided as follows:
INST "u_iodelay_ctrl/gen_idelayctrl_col0.u_idelayctrl_col0" LOC = "IDELAYCTRL_X2Y4"; # Bank # 36
INST "u_iodelay_ctrl/gen_idelayctrl_col1.u_idelayctrl_col1" LOC = "IDELAYCTRL_X1Y3"; # Bank # 24

In the above example, since the design spreads across two I/O columns, IDELYCTRL constraints are provided for two I/O columns.

* While providing the IDELAYCTRL LOC constraints, user should take care of the path of the constraints.
* For an example with these changes, please refer to the following test case which includes the MIG generated design files and modified files. Refer to the "readme.txt" file for more details on the various folders in attachment: http://www.xilinx.com/txpatches/pub/applications/misc/36554.zip

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
36211 MIG v3.5 - Release Notes and Known Issues for ISE Design Suite 12.2 N/A N/A
AR# 36554
Date 09/03/2014
Status Active
Type General Article
  • Virtex-6
  • MIG Virtex-6 and Spartan-6
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