The Virtex-6 FPGA MIG design uses a REFCLK of 300 MHz for designs running above 480 MHz and a REFCLK of 200 MHz for designs running below 480 MHz.
Consequently, it is possible for a MIG multi-controller output to have REFCLKs running at both 200 MHz and 300 MHz.
When this combination occurs, MAP incorrectly fails with the following message:
ERROR:PhysDesignRules:1613 - IDELAYCTRL not found for clock region CLOCKREGION_X0Y8. The IODELAYE1 block c0_u_memc_ui_top/
gen_loop_col0.u_odelay_rsync has an IDELAY_TYPE attribute of either FIXED or VARIABLE. This programming requires that there be an IDELAYCTRL block programmed within the same clock region.
More IDELAYCTRL resources are used in this scenario than are required.
This results in the following message in the MAP report file (*.mrp):
Number of IDELAYCTRLs: 72 out of 36 200% (OVERMAPPED)
This failure occurs in the following scenarios:
- DDR3 multi-controller designs where one controller frequency is 480 MHz and above and another controller frequency is below 480 MHz.
- Multi-Controller design with a DDR3 controller frequency above 480 MHz and a QDRII+ controller.
No failures occur for single controller designs and multi-controller designs containing only QDRII+.
The underlying reason for the failure is that the ISE software is not able to replicate IDELAYCTRLs for locked IODELAYs that do not have connectivity with IOBs (IODELAY-BUFIO and IODELAY-OLOGIC groups).
This issue is scheduled to be resolved in the ISE 12.3 implementation tools.
Until these tools are available, this Answer Record details the required work-around.