AR# 36593: Design Assistant for PCI Express - How Can I Check the Negotiated Link Width and Link Speed After Link Training?
Design Assistant for PCI Express - How Can I Check the Negotiated Link Width and Link Speed After Link Training?
How can I determine the negotiated link width and link speed after link training?
Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.
The negotiated link width and current link speed is contained in the Link Status register at offset 12h of the PCI Express Capability set. See section 7.8.8 of the PCI Base Specification for more information about this register.
There are mainly two ways to determine this information in hardware.
One is to use a tool such as PCITree or lspci to read the contents of the Link Status register. For more information about these types of software tools see (Xilinx Answer 34806) The Link Status register may be located at different locations depending on the core you are using. To find the location of the link status register, you can either following the linked capabilities list or look in the User Guide for the core in use. See (Xilinx Answer 35920) to help locate the correct User Guide. This information will be found the "Core Overview" section.
Another way to determine this information is to use the cfg_lstatus[15:0] output from the core to the user application.
In both cases, the current link speed is bits [3:0] and the negotiated link width is bits [9:4].
For current link speed a value of 0001b means the link is operating at 2.5 GT/s and 0010b means the link is operating at 5.0GT/s.
For the negotiated link with, a value of 000001b indicates x1, 000010b indicates x2, 000100b indicates x4, 001000b indicates x8.
Revision History 12/09/2010 - Corrected link width from [9:0] to [9:4] 08/13/2010 - Initial Release