We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 36633

Design Assistant for PCI Express - How can I know the values of the BARs after configuration?


How can I check the values of the BARs after configuration?

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express(Xilinx Answer 34536) TheXilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIeto guide you to the right information.


Coming out of reset the BAR registers will contain all zeroes in bits 31:4 of a memory BAR and bits 31:2 of an I/O BAR. The lower bits in each case have special meaning and may be one or zero depending on the BAR configuration. See Chapter 6 of the PCI Local Bus Specification for more information on how BARs work..

After the link is trained and the BIOS has enumerated and configured the devices, you can view the starting address in each of the endpoint's BARs. There are mainly two ways to do this.

In hardware, use a tool such as PCITree or lspci to read the contents of the Link Status register. For more information about these types of software tools see (Xilinx Answer 34806) The BARs are located at configuration address offsets 0x10 to 0x24.

You can also use the core's configuration access port to read the contents of the BAR registers. See the core's user guide for information on how to use this port. See (Xilinx Answer 35920) to help locate the correct User Guide.

Generally, you do not really need to know this information for normal operation of your design. The core does all the BAR decoding so it will inform the user app if a BAR has been hit and the TLP packet contains the address which can be treated as an offset from zero.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 36633
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • More
  • Virtex-6 SXT
  • Spartan-6 LXT
  • Less
  • Spartan-6 FPGA GTP Transceiver Wizard
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )