We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36677

Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 and v1.5 for PCI Express - Updated MGT Settings


This Answer Record contains updated MGT parameter settings for the v1.3 rev 2 core and the v1.5 core. These new settings provide a more stable link. These settings are valid for both ES and production silicon. ES silicon users should use ISE software12.1 or later and core version 1.3 rev 2. Production silicon users should use ISE software 12.1 or later and core version 1.5 or later.


Modify the parameters in the gtx_wrapper_v6.v[hd] file in the generated core's source directory to the following settings:

BIAS_CFG 17'h00000
RXEQMIX 10'b0110000011
PMA_RX_CFG 25'h05CE008
DFETAP1 5'd0
DFETAP2 5'd0
DFETAP3 4'd0
DFETAP4 4'd0

If the clocking is asynchronous, change PM_RX_CFG to be 25'h05CE049.For more information on clocking, see (Xilinx Answer 18329).

Revision History
07/20/2010- Corrected asynchronous setting
07/08/2010 - Initial Release

Linked Answer Records

Associated Answer Records

AR# 36677
Date 05/19/2012
Status Active
Type Known Issues
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 HXT
  • Virtex-6 CXT
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )