AR# 36677

Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 and v1.5 for PCI Express - Updated MGT Settings

Description

This Answer Record contains updated MGT parameter settings for the v1.3 rev 2 core and the v1.5 core. These new settings provide a more stable link. These settings are valid for both ES and production silicon. ES silicon users should use ISE software12.1 or later and core version 1.3 rev 2. Production silicon users should use ISE software 12.1 or later and core version 1.5 or later.

Solution

Modify the parameters in the gtx_wrapper_v6.v[hd] file in the generated core's source directory to the following settings:

BIAS_CFG	17'h00000
RX_EYE_OFFSET	8'h4C
RXEQMIX	10'b0110000011
PMA_RX_CFG	25'h05CE008
DFECLKDLYADJ	6'd0
DFETAP1	5'd0
DFETAP2	5'd0
DFETAP3	4'd0
DFETAP4	4'd0

If the clocking is asynchronous, change PM_RX_CFG to be 25'h05CE049.For more information on clocking, see (Xilinx Answer 18329).

Revision History
07/20/2010- Corrected asynchronous setting
07/08/2010 - Initial Release

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Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
18329	Endpoint for PCI Express - What clock frequency must be used when implementing a PCI Express solution in a Xilinx device?	N/A	N/A
33276	Virtex-6 FPGA Integrated Block Wrapper v1.3, v1.3 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1	N/A	N/A
35322	Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1	N/A	N/A

AR# 36677
Date	05/19/2012
Status	Active
Type	Known Issues
Devices	Virtex-6 LXT Virtex-6 SXT Virtex-6 HXT Virtex-6 CXT
IP	Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )

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AR# 36677

Virtex-6 FPGA Integrated Block Wrapper v1.3 rev 2 and v1.5 for PCI Express - Updated MGT Settings

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