BIAS_CFG | 17'h00000 |
RX_EYE_OFFSET | 8'h4C |
RXEQMIX | 10'b0110000011 |
PMA_RX_CFG | 25'h05CE008 |
DFECLKDLYADJ | 6'd0 |
DFETAP1 | 5'd0 |
DFETAP2 | 5'd0 |
DFETAP3 | 4'd0 |
DFETAP4 | 4'd0 |
Answer Number | Answer Title | Version Found | Version Resolved |
---|---|---|---|
18329 | Endpoint for PCI Express - What clock frequency must be used when implementing a PCI Express solution in a Xilinx device? | N/A | N/A |
33276 | Virtex-6 FPGA Integrated Block Wrapper v1.3, v1.3 rev 2 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 | N/A | N/A |
35322 | Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - Release Notes and Known Issues for ISE Design Suite 12.1 | N/A | N/A |