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AR# 36752

Virtex-6 MIG DDR2/DDR3 - Read/Write with Auto-Precharge


Are the write with auto-precharge and read with auto-precharge JEDEC commands supported by the MIG Virtex-6 DDR2/DDR3 design?

NOTE: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


The MIG Virtex-6 DDR2/DDR3 design does not support requesting a read with auto-precharge or write with auto-precharge from the User or Native Interface. The controller, however, does automatically issue these auto-precharge commands for bank management ensuring the highest possible efficiency.

The Virtex-6 DDR2/DDR3 reordering controller includes many features that ensure commands are executed in the most efficient manner.Bank management is one of these features. Multiple banks within a DDR2/DDR3 SDRAM device can be open at the same time. Keeping multiple banks open saves on cycles wasted for activates and precharges.The controller includes look-ahead logic to see the queue of commands requested. When the look ahead logic sees that a new row within a bank is going to be accessed, the Virtex-6 controller issues the last read/write to the currently opened row with an auto-precharge to ensure the highest efficiency.

The controller also sends auto-precharge commands when a maintenance command is required (i.e., Refresh or ZQ Calibration).

While the design does not expose the ability to auto-precharge to the user, writes and reads with auto-precharge are being issued by the controller to ensure the highest possible efficiency.

For additional information, refer to:
(Xilinx Answer 34905) - Virtex-6 DDR2/DDR3 Reordering Controller
(Xilinx Answer 34392) - Virtex-6 DDR2/DDR3 Controller Efficiency

AR# 36752
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
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