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AR# 36766

CPLD ISE 14.7 - Why do some signals appear as "X" when I perform Post FIT simulation?


When performing a Post FIT simulation, some registers are not initialized correctly and their output is seen as "X".

Why does this occur?


This is a known issue where the GSR is not being properly asserted in the VHDL simulation.

To work around this issue, switch your simulation language to Verilog.

If switching the simulation language does not work, then this is not the problem.

AR# 36766
Date 07/17/2017
Status Active
Type General Article
  • CPLD Device Families
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