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AR# 36766

CPLD ISE 12.1 - Why do some signals appear as "X" when I perform Post FIT simulation?


When performing a Post FIT simulation, some registers are not initialized correctly and their output is seen as "X".
Why does this occur?


This is a known issue where the GSR is not being properly asserted in the VHDL simulation.
To work around this issue,switchyour simulation language to Verilog.
Ifswitching thesimulation languagedoes not work, then this is not the problem.
AR# 36766
Date 12/15/2012
Status Active
Type General Article