We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36829

Design Assistant for PCI Express - Bus Master Enable, Memory, and IO enable bits must be set for TLPs to be transmitted or Received


This answer record describes common issues preventing the transfer and reception of TLPs.

Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.


To transfer TLPs onto he link, the Bus Master Enable bit which is bit 2 of the PCI Command register at address offset 0x04 in the configuration space must be set.

To receive memory or IO TLPs the memory or I/O enable bits, bits 0 and 1, must be set in the PCI Command register. If these bits are not set then the core will not accept the transfer.

This applies to MSI packets also since MSI packets are Memory Write TLPs. Note that this is true for both simulation and hardware, but the problem is most prevalent during simulation because it is generally taken care of by the system software in hardware without the user's intervention. However, in simulation the test bench must write these bits. For the endpoint, the root port must issue configuration writes to the endpoint to address 0x04 to set these bits. For the root port model, the user must send self configuration writes to the command register using the user application cfg port.

See Chapter 6 of the PCI Local Bus Specification v3.0 for more information about the PCI Command register.

Revision History
08/13/2010 - Initial Release

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34538 Xilinx Solution Center for PCI Express - Design Assistant N/A N/A
AR# 36829
Date 03/07/2013
Status Active
Type General Article
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
Page Bookmarked