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AR# 36919

12.1 System Generator - Block Error: Bool type output port y gets indeterminate value


When I run a simulation of a System Generator design, I run into the following error:

Block Error - (Source) - Bool type output port y gets indeterminate value

Why does this error occur and how can I resolve this issue?


Solution 1

SysGen does not appear to like having a Boolean output for the Slice8 block when using the Concat4 block as the output type of the Concat4 block is set to "double".

You can work around this by opening the Slice block and deselecting the Boolean output option, and then set the Width of slice = 1 as a workaround.

Solution 2

This error has been seen to occur erroneously when using Matlab 2009a. Upgrading to Matlab 2010a or newer resolves the issue.

Solution 3

This error has been observed while running the example design "QAM System with Packet Framing and FEC for Telemetry Channels" on the following hardware/software configurations:

Windows XP 32-bit, Matlab 2010a, ISE 12.3
Windows 7 64-bit, Matlab 2009b and 2010a, ISE 12.3

However, the issue does not occur on machines with the following configurations:

Windows XP 32-bit, Matlab 2009b, ISE 12.3
Windows XP 64-bit, Matlab 2010a, ISE 12.3
Linux 64-bit, Matlab 2010a, ISE 12.3

The issue is currently under investigation. To work around this error, run the design on machines that match the hardware/software configuration for known good runs shown above.

AR# 36919
Date 12/15/2012
Status Active
Type General Article
  • System Generator for DSP - 12.1
  • System Generator for DSP - 12.2
  • System Generator for DSP - 12.3