We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 36987

Virtex-6 FPGA Design Assistant - Designing block RAM and FIFO structures in Virtex-6 FPGAs


This Answer Record provides information on how to use the block RAM and FIFO blocks in the Virtex-6 FPGA fabric.
NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6.Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


The built in block RAM and FIFO primitives in the Virtex-6 FPGA can be used to implement RAMs, ROMs, and FIFO blocks for a design.The block RAM and FIFO are optimized for performance and allow you to implementa RAM, ROM, or FIFO block in a design without requiring large amounts of fabric resources from slice logic.
The Virtex-6 FPGA Memory Resources User Guide (UG363)provides additional details on the block RAM and FIFOs. It is recommended that you read through the user guides to familiarize yourself with its use and how they can be used in your design:
In addition, the following Answer Recordsare useful in providing details on different ways to implement block RAMs and FIFO blocks in your code:
(Xilinx Answer 37183) - How to infer the use of Block RAM and FIFO primitives in your HDL code
(Xilinx Answer37184) - Using block RAM CORE Generator and FIFO CORE Generator to setup the blocks for use in HDL code

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

AR# 36987
Date 12/15/2012
Status Active
Type General Article
Page Bookmarked