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AR# 37023

MIG v3.0-3.4, Virtex-6, DDR2/DDR3 - app_wdf_rdy signal stuck Low


The write data is registered in the write FIFO when app_wdf_wren is asserted and app_wdf_rdy is High. "app_wdf_wren" is the active-High strobe for "app_wdf_data[]", and "app_wdf_end" is the active-High input that indicates the last cycle of input data for "app_wdf_data[]". "app_wdf_end" should not be treated as a "don't care" when "app_wdf_wren" is Low and the write timing diagrams in UG406 should be exactly followed to ensure correct operation of the controller. If the write timing commands are not followed exactly, you might see the "app_wdf_rdy" signal become stuck Low.


"app_wdf_end" should only be asserted when "app_wdf_wren" is High just as the timing diagrams in UG406 illustrate. If "app_wdf_end" is asserted while "app_wdf_wren" is Low, then this can cause an underflow condition to occur for the Write FIFO counter and cause "app_wdf_rdy" to become stuck Low, preventing the you from performing any other commands.
MIG v3.5 has shown to fix the problem for some instances, but not for all, so it is important that you follow the write timing diagram exactly as it is shown in UG406.
AR# 37023
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
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