General Description: Xilinx has evaluated the quality of results for VHDL designs targeted to XC9500 CPLDs that are compiled using Foundation Express and FPGA Express. Through our benchmarking, we have established a set of recommendations for compiling VHDL designs in the form of suggested synthesis and fitter options. This combination of settings provides the best quality density and performance results for the largest number of our test designs. This is not to say that these settings will provide the best results in every situation, but the recommendations will generally allow the best results to be obtained.
1. In FPGA Express, use AREA optimization when synthesizing. 2. In FPGA Express, use BINARY encoding for FSMs. 3. In the CPLD Fitter (Design Manager), use the "Optimize for Speed" Implementation Template, and set the Pterm Collapse limit to 90.
Details for using these settings:
1. AREA optimization in FPGA Express When you create an implementation in FPGA Express, select "Optimize for Area" in the Create Implementation dialog box.
2. BINARY encoding for FSMs - From within FPGA Express, select Synthesis -> Options -> Project. - Under "Default FSM Encoding", select Binary. Note that you must re-analyze the design for this setting to take effect. To re-analyze, select Synthesis -> Force Update.
3. Optimize the Fitter for Speed; Pterms=90 - From within the Design Manager, implement the design. - When the Implement dialog box appears, select the Options button. - In the Options dialog box, select the pull-down menu under "Implementation Program Option Templates", and choose "Optimize Speed". - Select "Edit Template" and go to the Advanced Optimization tab. Change the Collapsing Pterm Limit to 90.