Known Issues / Limitations: * Virtex-6 DDR2/DDR3 memory interfaces do not support 64 bit physical memory.
But the configureGUI for the mpmc allows the selection of the MT9JSF12872XX-1G1.
The MPMC GUI will allow you to select a 64-bit memory interface device, but this is only allowed for designs that will use half of the memory device. So, essentially, you will still only get 32-bit (C_MEM_DATA_WIDTH <= 32) interface.
This limitation is caused by the MPMC FIFO's being limited to 128-bit single data rate, whereas the MIG PHY standaloneis 256-bit wide SDR interface compatible. The SDR rate is important because the MIG PHY divides the double rate input into single data inorder to reduce controller clock frequency.
At this time there is not any scheduled support for 64-bit DDR3 interface on the existingMPMC Core for Virtex-6 devices. MPMC is replaced by an AXI-only MIG controller (AXI_V6_DDRx) starting in EDK 12.3 which supports 64-bit DDR2/DDR3 interfaces in Virtex-6 FPGA.