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AR# 37065

Virtex-6 FPGA Design Assistant - Setting logic controls in the fabric


This Answer Record provides an explanation on using flip-flop and logic controls that can be set to help improve performance of your design.
NOTE: This Answer Record is a part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


There are many primitives in the Virtex-6 FPGA fabric that can be used with Set/Reset control, clock enables, and other logic control functions.These types of logic control can either be inferred in your logic or instantiated manually.
Clock Enable
For clocks in your design, you should always use clockenables when available in order to save your clock resources, improve timing characteristics, and reduce power. If you want to enable a clock onan entire clock tree, you can use the clock enable available on BUFGs.If only registers need to be enabled, use the individual clock enable controls that are available in the registers.
When using a set or reset function in your design, always use the set or reset synchronously. Using an asynchronous reset can result in degraded performance as the synthesis tools cannot perform optimizations as easily.For other control ports used in different primitives, synchronous control should be used for the same reason since asynchronous operation limits optimization during synthesis.
Please read over the HDL Coding Practices to Accelerate Design Performance White Paper (WP231)as it discusses in detail coding practices that should be used to optimize performance with your design:
In addition, the Virtex-6 User Guides describe the primitives and blocks (blockRAM, CLB, MMCM, buffers, etc.) in more detail so that you have a better understanding of how the Virtex-6 FPGA fabric can work for you in a design.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36986 Virtex-6 FPGA Design Assistant - Designing configurable logic structures in Virtex-6 FPGAs N/A N/A
AR# 37065
Date 12/15/2012
Status Active
Type General Article
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