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AR# 37066

Virtex-6 FPGA Design Assistant - Using SRLs to conserve resources


This Answer Record discusses how shift register look-up tables (SRLs) can be used to help conserve resources in fabric.
NOTE: This Answer Record is a part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963) Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices. Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.


The SRL primitive can be used to reduce resources used in a design.Instead of implementing a shift register using a series of flip-flops, you can implement a shift register in the dedicated performance optimized SRL blocks in fabric.However, in order to use an SRL in your design, you must be careful how you use resets.
Resets should not be used on shift registers in your design as this requires additional logic around the SRL block which reduces performance and increases the amount of logic needed to implement the shift register.
For more information on using SRLs in your design, see the section on SRLs in the HDL Coding Practices to Accelerate Design Performance White Paper (WP231):

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34963 Xilinx Virtex-6 FPGA Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
36986 Virtex-6 FPGA Design Assistant - Designing configurable logic structures in Virtex-6 FPGAs N/A N/A
AR# 37066
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
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