Xilinx PlanAhead Tool Solution Center
The PlanAhead Tool Solution Center is available to address all questions related to the PlanAhead tool. Whether you are learning how to use the tool or troubleshooting a problem, use the PlanAhead Tool Solution Center to guide you to the right information.
Design Assistant
Xilinx PlanAhead Tool Solution Center - Design Assistant
ThePlanAhead Tool Design Assistant will walk you through the different flows available in the PlanAhead tool while debugging commonly encountered issues such as floorplanning and pin placement failures. The Design Assistant will not only provide useful design and troubleshoot information but also point you to the exact documentation you need to read to help you use the PlanAhead tool efficiently.NOTE:This answer record is part of the Xilinx PlanAhead Tool Solution Center(Xilinx Answer 37100). The Xilinx PlanAhead Tool Solution Center is available to address all questions related to the PlanAhead tool. Whether you are starting a new design with the PlanAhead tool or troubleshooting a problem, use the PlanAhead Tool Solution Center to guide you to the right information.
First, select the topic for which you have a question or are troubleshooting an issue related to your PlanAhead tool design. This will ensure the PlanAhead Tool Design Assistant points you to the information you need to continually move forward with your design.
(Xilinx Answer 37380) - Functionality and Usage
(Xilinx Answer 37381) - Features
(Xilinx Answer 37379) - Error/Warning Codes
(Xilinx Answer 37382) - Quality of Results
Documentation
Xilinx PlanAhead Tool Solution Center - Documentation
Please refer to the following documentation when using the PlanAhead tool.
NOTE: This answer record is part of the Xilinx PlanAhead Tool Solution Center (Xilinx Answer 37100). The Xilinx PlanAhead Tool Solution Center is available to address all questions related to the PlanAhead tool. Whether you are starting a new design with the PlanAhead tool or troubleshooting a problem, use the PlanAhead Tool Solution Center to guide you to the right information.
12.1 PlanAhead General Resources
- What's New in PlanAhead 12.1 - UG656
- PlanAhead User Guide - UG632
- PlanAhead Floorplanning Methodology Guide - UG633
- Hierarchical Design Methodology Guide - UG748
12.1 PlanAhead Tutorials
- Quick Front-to-Back Overview - UG673
- Design Analysis and Floorplanning - UG676
- I/O Pin Planning - UG674
- RTL Design and IP Generation with CORE Generator - UG675
- Debugging with Chipscope - UG677
- Leveraging Design Preservation for Predictable Results - UG747
Design Advisories
PlanAhead Solution Center - Design Advisory
Design Advisory Answer Records are created for issues that are important to designs currently in progress and can be selected to be included in the Xilinx Alert Notification System.NOTE: This Answer Record is part of the Xilinx PlanAhead Solution Center (Xilinx Answer 37100). The Xilinx PlanAhead Solution Center is available to address all questions related to PlanAhead. Whether you are starting a new design with PlanAhead or troubleshooting a problem, use the PlanAhead Solution Center to guide you to the right information.
Design Advisories
3/19/2011 - (Xilinx Answer 41128)- 13.1 PlanAhead - Import ISE Project sets the -r (Ignore Location Constraints) option for NGDBUILD
Revision History
3/19/2011 - Added AR 41128
Top Issues
Xilinx PlanAhead Tool Solution Center - Top Issues
The following answer records cover current known issues as well as commonly asked questions related to the PlanAhead tool.
NOTE: This answer record is part of the Xilinx PlanAhead Tool Solution Center (Xilinx Answer 37100). The Xilinx PlanAhead Tool Solution Center is available to address all questions related to the PlanAhead tool. Whether you are starting a new design with the PlanAhead tool or troubleshooting a problem, use the PlanAhead Tool Solution Center to guide you to the right information.
Known Issues
(Xilinx Answer 34799) 12.1 PlanAhead Known Issues
(Xilinx Answer 36167) 12.2 PlanAhead Release Notes
Top Issues
(Xilinx Answer 34878) 12.1 PlanAhead - "ERROR: [HD-UCFReader 1] Unrecognized symbol \/leaf_2\/cont_ram\/v16384x72/BU2132"
(Xilinx Answer 35743) 12.1 PlanAhead - Incorrect BIVB DRC errors from PlanAhead
(Xilinx Answer 34793) 12.1 PlanAhead - Synthesis with a netlist as top level in an RTL Project
(Xilinx Answer 34858) 12.1 PlanAhead - Error on constraints when running Implementation in PlanAhead points to merged .ucf
(Xilinx Answer 34876) 12.1 PlanAhead - "RTL I/O Planner view" errors on LOC constraints