AR# 37173: MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3
AR# 37173
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MIG v3.6 - Release Notes and Known Issues for ISE Design Suite 12.3
Description
This Release Notes and Known Issues Answer Record is for the Memory Interface Generator (MIG) v3.6 released in ISE Design Suite 12.3 and contains the following information:
PROHIBIT constraints added on unused DQSN/UDQSN pins in UCF in case of single-ended DQS designs
CR 552374
Added 2Gb memory parts support for DDR3 designs
CR 568940
Added new parameter to differentiate between input and memory clock
CR 570186
Reset signal (DDR3_Reset) voltage standard changed to LVCMOS15 from SSTL15
CR 564152
Spartan-3 Generation
(Xilinx Answer 36553) MIG v3.5, Spartan-3A DSP DDR SDRAM - MAP fails on MIG output design when synthesized using Synplicity
Known Issues
Virtex-6 MIG Designs (Xilinx Answer 37968) MIG v3.6 Virtex-6 DDR2/DDR3 - Additional calibration stage (CLKDIV Calibration Stage) added to calibrate the timing of the BUFIO to BUFR transfer (Xilinx Answer 37861) MIG v3.6, Virtex-6 DDR3 - Multi-Controller VHDL designs may exhibit data errors in simulation when targeting an RDIMM (Xilinx Answer 37863) MIG v3.6, Virtex-6 Multi-Controller - Default bank selection for all FF1760 packages results in MAP error (Xilinx Answer 37997) MIG v3.6 Virtex-6 DDR3 Multi-Controller - GUI only allows single controller generation for CXT -1 devices (Xilinx Answer 38083) MIG v3.6, Virtex-6 DDR3 - Multi-Controller Verilog designs are failing in simulation when targeting a UDIMM whose base part is x16 (Xilinx Answer 38104) MIG v3.6, Virtex-6 - GUI does not allow AXI RDIMM data width selection. (Xilinx Answer 38111) The Design Notes include incorrect statements regarding rank support and hardware testbench support. (Xilinx Answer 38125) MIG v3.6, Virtex-6 DDR2/DDR3 - MIG v3.6, Virtex-6 DDR2/DDR3 - comments in the UCF are incorrect.