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Xilinx High-Speed Serial I/O Solution Center




The High Speed Serial I/O (HSSIO) Solution Center is a resource to help answer any questions related to the Xilinx Multi-Gigabit Transceivers.

Whether implementation, board level, or any other aspect of the design process, the Solution Center aims to guide you to the correct information.

Design Assistant

Xilinx HSSIO Solution Center - Design Assistant

The Design Assistant will walk you through the recommended design flow for HSSIO while debugging commonly encountered issues.

The Design Assistant not only provides useful design and troubleshoot information, but also points you to the exact documentation you need to read to help you design efficiently with HSSIO.

Note: This answer record is part of Xilinx HSSIO Solution Center (Xilinx Answer 37181). The Xilinx HSSIO Solution Center is available to address all questions related to HSSIO.

Whether you are starting a new design or troubleshooting a problem, use the HSSIO Solution Center to guide you to the right information.

This answer record presents a structured guide to using the Xilinx High Speed Serial Transceivers.

Below you will find links to documentation, support resources, and targeted answer records guiding each step of the transceiver design creation.

These are the Xilinx devices containing serial transceivers:

  • Virtex-II Pro
  • Virtex-4 FX
  • Virtex-5 LXT, SXT, FXT
  • Virtex-5Q LXT, SXT, FXT
  • Virtex-5QV FX130
  • Virtex-6 LXT, SXT, CXT, HXT
  • Spartan-6 LXT
  • Spartan-6Q LXT
  • Artix-7 LXT
  • Kintex-7 LXT
  • Virtex-7 LXT, HXT
  • Kintex-UltraScale
  • Virtex-UltraScale


Each of these devices has an associated user guide which details the features and use of the serial transceivers in them. 

These guides can be found on the Xilinx Documentation page at:

http://www.xilinx.com/support.html

To obtain alerts for any documentation, please sign-up here:

Sign up for alerts - You especially want to stay up-to-date on the latest Design Advisories for your product.

Likewise, many product families have a master answer record to assist in tracking known issues:

Xilinx also provides community forums and training to help designers better understand these products:

For guidance on using and debugging serial transceivers beyond these resources, please select the answer record below that is most relevant to your question(s).


Xilinx encourages the following design flow for incorporating serial transceivers into a design:

(Xilinx Answer 57259) Creating the HSSIO with the Wizard Every HSSIO design should be started by using the appropriate wizard to create an example design approximating the intended functionality of the link.
Details on how to select appropriate settings are given in this answer record, the wizard user guide, and the transceiver user guide.
(Xilinx Answer 57260) Design Implementation Once suitable IP has been generated by the wizard, it should then be used to create an example design and incorporated into the actual design logic it is meant for.
Some modifications might be necessary, but the vast majority of MGT settings should be left to the wizard.
This answer record contains guidance on going through this process.
(Xilinx Answer 57261) Digital Simulation Along with the example design, the transceiver wizard provides wrappers around a digital simulation model of the transceiver.
This can be used to accurately simulate the transceiver bring-up, resets, and interaction with user logic.
Digital simulation should be performed to verify the behavior of the transceiver in your design.
(Xilinx Answer 57191) Electrical Simulation Electrical simulation pertains to verifying the integrity of your physical link. Signal integrity can be simulated using Xilinx-provided IBIS-AMI models.
Details on how to perform your own simulations are given in this answer record.
(Xilinx Answer 57237) Debugging When a transceiver design is not working as intended, there are many factors to consider when looking for a solution.
This answer record will help guide you in that process.

Documentation

High-Speed Serial Transceiver Documentation

This answer record contains a list of all of the documentation that is relevant to High Speed Serial Applications using the Xilinx Multi-Gigabit Transceivers.

It includes user guides, data sheets, errata with transceiver-related items, application notes, and white papers.

UltraScale

7 Series

Virtex-6

Spartan-6

Virtex-5

Virtex-4

Virtex-II Pro

Application Notes

Application notes for the Xilinx RocketIO and High-Speed Transceivers fall into one of three categories:

1) Serial Digital Interface Application Notes

2) Serial IO Application Notes

3) Protocol Specific Application Notes:

White Papers

White papers for the Xilinx RocketIO and High-Speed Transceivers fall into one of two main categories:

1) Serial Digital Interface White Papers

2) Protocol Specific White Papers:

Relevant Errata

UltraScale

7 Series

Virtex-6

Spartan-6

Virtex-5

Virtex-4 FXT

Virtex-II Pro X


Design Advisories

Design Advisories for High Speed Serial Transceivers

Design Advisory Answer Records are created for issues that are important to designs currently in progress, and are selected to be included in the Xilinx Alert Notification System.


Design Advisory Answer Records discuss new issues that are relevant to designs currently in progress.

Users can be informed of relevant HSSIO design advisories by signing up for specific silicon families in the Xilinx Alert Notification System.

To update your Xilinx Alert Notification Preferences, go to: http://www.xilinx.com/support/myalerts.

Design Advisory Master Answer Records


(Xilinx Answer 61930) Design Advisory Master Answer Record for Virtex UltraScale FPGA
(Xilinx Answer 51456) Design Advisory Master Answer Record for Artix-7 FPGA
(Xilinx Answer 42944) Design Advisory Master Answer Record for Virtex-7 FPGA
(Xilinx Answer 42946) Design Advisory Master Answer Record for Kintex-7 FPGA
(Xilinx Answer 34856) Design Advisory Master Answer Record for Spartan-6 FPGA
(Xilinx Answer 34565) Design Advisory Master Answer Record for the Virtex-6 FPGA

Top Issues

High-Speed Serial Transceivers - Top Issues

This answer record lists some of the top and known issues for high-speed serial transceivers across FPGA families that designers might need to be aware of.

Transceiver Family-Specific Known Issues


(Xilinx Answer 62670) UltraScale FPGAs GTH Transceiver - Known Issues and Answer Record List
(Xilinx Answer 64440) UltraScale FPGAs GTY Transceiver - Known Issues and Answer Record List
(Xilinx Answer 47852) 7 Series FPGA GTP Transceiver Known Issues and Answer Record List
(Xilinx Answer 41613) 7 Series FPGA GTX/GTH Transceiver Known Issues and Answer Record List
(Xilinx Answer 38596) Virtex-6 FPGA GTH Transceiver Known Issues and Answer Record List
(Xilinx Answer 33475) Virtex-6 FPGA GTX Transceiver Known Issues and Answer Record List
(Xilinx Answer 33487) Spartan-6 FPGA GTP Transceiver Known Issues and Answer Record List
(Xilinx Answer 31458) Virtex-5 FPGA GTX RocketIO Transceiver Answer Record List
(Xilinx Answer 24367) Virtex-5 FPGA GTP RocketIO Transceiver Answer Record List
(Xilinx Answer 21004) Virtex-4 FPGA RocketIO Transceiver Answer Record List
(Xilinx Answer 21006) Virtex-II Pro FPGA RocketIO Transceiver Answer Record List


Top Issues

UltraScale



(Xilinx Answer 63026) UltraScale GTH Transceiver - Reference clock phase noise mask
(Xilinx Answer 65111) UltraScale RX/TXUSRCLK routing
(Xilinx Answer 64062) UltraScale GTY RX reset in Near End PMA loopback (TX->RX serial loopback)
(Xilinx Answer 62527) UltraScale GTY - How to set the CDR to "lock to local reference clock"
(Xilinx Answer 64103) UltraScale GTH/GTY TX/RX PROG DIV block reset requirements
(Xilinx Answer 61723) UltraScale GTH and GTY transceivers reference clock AC coupling capacitor value
(Xilinx Answer 63391) My UltraScale GTY line rate violates the minimum value in Table 58 of the data sheet
(Xilinx Answer 64201) UltraScale Transceivers - When is the use of OBUFDS_GTE3 recommended or required?
(Xilinx Answer 63704) UltraScale GTH/GTY - How to switch to use internal PRBS pattern generator when using Async Gearbox mode
(Xilinx Answer 64012) Synchronous gearbox normal (non-CAUI) usage for 128-bit fabric interface (64-bit internal) UltraScale GTY
(Xilinx Answer 61946) Virtex UltraScale GTY - UG578 v1.0 - incorrect description for reference clock selection above 16.375 Gbps
(Xilinx Answer 62261) Datarate limitation for GTY TX Phase Interpolator usage
(Xilinx Answer 64838) Design Advisory for UltraScale FPGA Transceivers Wizard: GTH Production Updates In Vivado 2015.2
(Xilinx Answer 64309) UltraScale GTH Transceiver: TX and RX latency values
(Xilinx Answer 59834) My UltraScale device package is showing 2 power groups for the MGT power supplies when there is only one column of GTs
(Xilinx Answer 63622) UltraScale FPGA Transceivers Wizard v1.5 - Release Notes and Known Issues
(Xilinx Answer 62527) UltraScale GTY: How to set the CDR to "lock to local reference clock"
(Xilinx Answer 65528) How to share a COMMON block using GTH transceivers
(Xilinx Answer 62548) My GTY/GTH refclk output is not toggling
(Xilinx Answer 64351) Vivado Constraints - How to constrain Gigabit Transceiver output Clocks


7 Series


(Xilinx Answer 42662) 7 Series GTX Transceiver - TX and RX Latency Values
(Xilinx Answer 46490) 7 Series GTH Transceiver - TX and RX Latency Values
(Xilinx Answer 58981) 7 Series GTP Transceiver - TX and RX Latency Values
(Xilinx Answer 47443) Design Advisory for 7 Series FPGAs GTH Transceiver Power-Up/Power-Down
(Xilinx Answer 47817) Design Advisory for the Kintex-7 and Virtex-7 GTX Transceiver Power-Up/Power-Down
(Xilinx Answer 51017) 7 Series FPGA GTP Transceiver Power-Up/Power-Down
(Xilinx Answer 47328) 7 Series GTX-Loopback mode known limitations
(Xilinx Answer 43482) 7 Series GTX Transceivers - Reset requirements upon configuration
(Xilinx Answer 45598) 7 Series FPGA GTX/GTH Transceivers - Quad Usage Priority Information
(Xilinx Answer 47331) 7 Series FPGA GTX/GTH Transceivers - No Power Sequencing Requirement for MGTAVTT/MGTVCCAUX
(Xilinx Answer 50299) 7 Series FPGAs Transceivers Wizard and Aurora 8B10B/64B66B Cores - Support for GTX Transceivers in Zynq Devices
(Xilinx Answer 50890) 7 Series FPGAs Transceivers Wizard Flow in Vivado Design Suite 2012.2
(Xilinx Answer 46048) 7 Series FPGAs Transceivers Wizard - What silicon revisions are supported by different Wizard or ISE design tool versions?
(Xilinx Answer 43244) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon
(Xilinx Answer 45360) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon
(Xilinx Answer 45410) 7 Series FPGA GTX Transceivers - Initial ES to General ES Silicon GTX Migration
(Xilinx Answer 47128) Design Advisory for the Virtex-7 FPGA GTH Transceiver - Attribute Updates and Use Modes for Initial Engineering Sample (ES) Silicon
(Xilinx Answer 50617) Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers
(Xilinx Answer 51369) Design Advisory for the Artix-7 FPGA GTP Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon
(Xilinx Answer 43339) 7 Series FPGA GTX Transceiver Software Use Model Changes


Virtex-6

(Xilinx Answer 40902) Virtex-6 FPGA GTH Transceiver - Updates for Production HXT; attributes and initialization sequences
(Xilinx Answer 41464) Virtex-6 HXT Devices - How do I Identify ES vs. Production Silicon?
(Xilinx Answer 42987) Virtex-6 FPGA GTH Transceiver - Reference clock phase noise mask
(Xilinx Answer 38564) Virtex-6 GTX - Variation in analog power supply voltage while powering up or down transceivers
(Xilinx Answer 38506) Virtex-6 FPGA GTX Transceiver - Reference clock phase noise mask
(Xilinx Answer 39430) Virtex-6 GTX Transceiver - Delay aligner errata and work-around
(Xilinx Answer 35055) Virtex-6 FPGA GTX Transceiver - Automatic Macro Insertion for Unused GTX Transceivers
(Xilinx Answer 34191) Virtex-6 FPGA GTX Transceiver Wizard - Attribute updates for production silicon
(Xilinx Answer 35681) Virtex-6 GTX Transceiver - MMCM fails to lock and TX/RXRESETDONE fails to assert
(Xilinx Answer 34192) Virtex-6 GTX Transceiver Wizard - Oversampling rate update for production silicon
(Xilinx Answer 34028) Virtex-6 GTX Transceiver - Instantiating a dummy transceiver to allow for correct calibration


Spartan-6


(Xilinx Answer 43154) Spartan-6 FPGA GTP Transceiver - Reference clock phase noise mask
(Xilinx Answer 35776) Spartan-6 GTP Transceiver - Recommended PMA_CDR_CFG settings for improved CDR performance
(Xilinx Answer 35237) Spartan-6 FPGA GTP Transceiver - SelectIO to GTP Crosstalk/SSO Guidelines
(Xilinx Answer 35434) Spartan-6 GTP Transceiver - Updates for production silicon


Virtex-5


(Xilinx Answer 30915) Virtex-5 GTP RocketIO - MGTAVCC Power recommendations for unused tiles between calibration resistor and instantiated tiles
(Xilinx Answer 31968) Virtex-5 GTX RocketIO - Rate change implementation steps


Software

(Xilinx Answer 22088) 7.1i MAP - "WARNING:PhysDesignRules:367 - The signal <DESIGN_MODULE/TXN> is incomplete"


General

(Xilinx Answer 37954) High Speed Serial Transceivers - Powering unused transceivers