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AR# 37202

Virtex-4 Aurora 8b/10b - I cannot select REFCLK1 in column 2


When only MGT(s) in column1 are selected, the REFCLK selection automatically goes to REFCLK2. When you change this to REFCLK1, the CORE Generator software can show the following behavior:

  • In ISE Design Suite 11.4, it automatically changed the REFCLK selection back to REFCLK2.
  • From ISE Design Suite 12.1 on, the CORE Generator software generates the following errors:
    • "ERROR:sim - c_mgt_clock_1: Invalid value 'None'."
    • "ERROR:sim lane 2 should be assigned"


This is an issue in the CORE Generator software and not in the Aurora core itself. It shows up onlyin the CORE Generator software in ISE Design Suite 11.3 and above.

To work around this issue, generate the Virtex-4 Aurora core in ISE Design Suite 11.2. Version 3.1 of the Virtex-4 Aurora core was already available in 11.2, so the latest version is still being used.

It isbest to use the latest version of ISE. Since the Aurora core generates the HDL files, it is no problem to create a project in the latest version of ISE software while using the Aurora files from a previous version.

AR# 37202
Date 12/15/2012
Status Active
Type General Article
  • Aurora 8B/10B Virtex-4 FX
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