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AR# 37207

Design Advisory for the Virtex-6 FPGA Integrated Block Wrapper v1.5 for PCI Express - x8 Gen 2 128-bit Wrapper is Not Deasserting trn_tdst_rdy_n When Integrated Block Transmit Buffer is Full


Known Issue: v1.5, v1.4, v1.3.2, v1.3.1, v1.3

The x8 Gen 2 128-bit wrapper is not deasserting trn_tdst_rdy_n when the integrated block's transmit buffer is full. This is causing packets provided to the wrapper by the user application to be lost.


Fix this problem by downloading a fixed version of the wrapper source file trn_tx_128.v[hd]. Download this file from (Xilinx Answer 34279). The update is called ar37207_v6_pcie_v1_5_update1.zip.

The fixed version of this file will be included with the v1.6 release of the Virtex-6 Inetgrated Block's wrapper release in ISE software 12.3.

Revision History
07/05/2011 - Updated title
08/04/2010 - Initial Release

Linked Answer Records

Master Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33775 Design Advisory Master Answer Record for the Virtex-6 FPGA Integrated Block Wrapper for PCI Express N/A N/A
AR# 37207
Date 05/20/2012
Status Active
Type Design Advisory
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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