This Answer Record can be used as a starting point to guide you through troubleshooting common problems that might be encountered in Virtex-6 FPGA designs. NOTE: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices.Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.
If you are having trouble finding a solution to an issue youare having with a Virtex-6 FPGA design, choose from the following categories that best fits your issue: Clocking (Xilinx Answer 37212)- Refer tothisAnswer Record for common issues with MMCMs and clocking structures/routing.This Answer Record helps walk you through debug techniques that can resolve some of the common clocking problems. Fabric Debug (Xilinx Answer 37213)- Refer to this Answer Record forcommon issues relating to the CLB in fabric.ThisAnswer Record helps walk you through debug techniques that can resolve some of the common fabric related problems. Block RAM/FIFO (Xilinx Answer 37214)- Refer to this Answer Record for common issues relating to theblock RAM or FIFOin fabric.This Answer Record helps walk you through debug techniques that can resolve some of the common block RAM/FIFO related problems.