This Answer Record helps guide you to solutions to common problems with the fabric resources in Virtex-6 FPGA designs.
Note: This Answer Record is part of the Xilinx Virtex-6 FPGA Solution Center (Xilinx Answer 34963).
The Xilinx Virtex-6 FPGA Solution Center is available to address all questions related to Virtex-6 devices.
Whether you are starting a new design with Virtex-6 FPGA or troubleshooting a problem, use the Virtex-6 FPGA Solution Center to guide you to the right information.
Select from the following list of common fabric related problems.
Each Answer Record helps guide you to a solution.
|(Xilinx Answer 34120)||Inversion not pushed into Output FF input|
|(Xilinx Answer 32987)||What options are available that allow two SRL16s to be combined into one LUT Complex?|
|(Xilinx Answer 34164)||Virtex-6 FPGA designs must be re-run through implementation in ISE 11.5 or later software|