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AR# 37252

Xilinx Configuration Solution Center - Configuration Design Advisories

Description

The Configuration Design Advisory Answer Records (DAARs) are created for issues that are important to designs currently in progress, and you can select them to be included in the Xilinx Alert Notification System.

Note: To update your Xilinx Alert Notification Preferences, go to: https://www.xilinx.com/support/myalerts.

This Answer Record is part of the Xilinx Configuration Solution Center (Xilinx Answer 34904)

Solution

UltraScale and UltraScale+:

For a comprehensive list on Design Advisories for UltraScale FPGAs, please refer to the Master Answer Record links below

 

(Xilinx Answer 61598) Design Advisory Master Answer Record for Kintex UltraScale FPGAs
(Xilinx Answer 61930) Design Advisory Master Answer Record for Virtex UltraScale FPGAs

 

UltraScale and UltraScale+:

 

Design Advisories Alerted on April 10th, 2017
(Xilinx Answer 68832) Design Advisory for UltraScale FPGA, UltraScale+ FPGA, and Zynq UltraScale+ MPSoC eFUSE Programming with Vivado 2016.4 (and earlier)
Design Advisory Alerted on December 19th, 2016
(Xilinx Answer 67645) Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation
Design Advisories Alerted on November 1st, 2016
(Xilinx Answer 68006) Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly
Design Advisory Alerted on December 21st, 2015
(Xilinx Answer 65792) Design Advisory for UltraScale RSA Authentication - UltraScale devices that use RSA authentication will fail bitstream authentication when smaller configuration interface widths are used.
Design Advisories Alerted on November 10, 2014
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGA

 

7 Series:

For a comprehensive list of Design Advisories for 7 Series FPGAs, please refer to the Master Answer Record links below

(Xilinx Answer 42944) Design Advisory Master Answer Record for Virtex-7 FPGAs
(Xilinx Answer 42946) Design Advisory Master Answer Record for Kintex-7 FPGAs
(Xilinx Answer 51456) Design Advisory Master Answer Record for Artix-7 FPGAs

 

Virtex-7 Configuration Specific Design Advisories:

Design Advisories Alerted on December 19, 2016
(Xilinx Answer 67645) Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation
Design Advisories Alerted on November 10, 2014
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 Series and UltraScale FPGAs
Design Advisories Alerted on November 5, 2012
(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode
Design Advisories Alerted on August 20, 2012
(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices

 

Kintex-7 Configuration Specific Design Advisories

Design Advisories Alerted on December 19, 2016
(Xilinx Answer 67645) Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation
Design Advisories Alerted on November 10, 2014
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 Series and UltraScale FPGAs
Design Advisories Alerted on April 3, 2013
(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT - Bitstream compatibility requirements between GES and Production devices: Updated for 7V690T production devices
Design Advisories Alerted on November 5, 2012
(Xilinx Answer 50906) Updated Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices; updated for 14.3/2012.3 release
Design Advisories Alerted on October 29, 2012
(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode
Design Advisories Alerted on October 22, 2012
(Xilinx Answer 50617) Updated the bitstream compatibility section in the Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceiver
Design Advisory Alerted on October 17, 2011
(Xilinx Answer 44421) Design Advisory for 13.2 iMPACT - Incorrect indirect programming core file is loaded to Kintex-7 leading to potential device damage

 

Artix-7 Configuration Specific Design Advisories

Design Advisories Alerted on December 19, 2016
(Xilinx Answer 67645) Design Advisory for 7 Series and UltraScale Architecture FPGA configuration fallback and POST_CRC limitation
Design Advisories Alerted on October 31st, 2016
(Xilinx Answer 68006) Design Advisory for Xilinx Design Tools (Vivado, SDAccel, SDSoC) 2016.1 and 2016.2 write_bitstream - Multi-threading might cause configuration memory cells to be set incorrectly
Design Advisories Alerted on November 10, 2014
(Xilinx Answer 62631) Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 Series and UltraScale FPGAs
Design Advisory Alerted on August 26, 2013
(Xilinx Answer 57045) Design Advisory for Artix-7/Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration
Design Advisory Alerted on October 29, 2012
(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode

 

Older Architectures

For a comprehensive list on Design Advisories for 6 Series FPGAs, please refer to the Master Answer Record links below:

(Xilinx Answer 34565) Design Advisory Master Answer Record for Virtex-6 FPGA
(Xilinx Answer 34856) Design Advisory Master Answer Record for Spartan-6 FPGA

 

Virtex-6 Configuration Specific Design Advisories

Design Advisory Alerted on August 13, 2012:
(Xilinx Answer 51145) Design Advisory - 14.2 iMPACT - Indirect Programming on Virtex-6 causes tool to crash without warning
Design Advisories Alerted on August 8, 2011:
(Xilinx Answer 42682) Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain
Design Advisories Alerted on July 11, 2011:
(Xilinx Answer 41821) Design Advisory for Virtex-6 FPGA - BitGen Option -g Next_Config_Addr: Default Value Changed
Design Advisories Alerted on July 6, 2011:
(Xilinx Answer 42682) Design Advisory for Virtex-6 FPGA - 13.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain
Design Advisories Alerted on October 18, 2010:
(Xilinx Answer 38134) Virtex-6 Configuration - PROGRAM_B pin held Low prior to power up does not delay configuration

 

Spartan-6 Configuration Specific Design Advisories

Design Advisory Alerted on June 19, 2013
(Xilinx Answer 56363) Design Advisory for Spartan-6 FPGAs - JTAG Boundary Scan testing can fail with inverted values seen on pins when the device is configured
Design Advisory Alerted on April 02, 2013
(Xilinx Answer 55037) Design Advisory for Spartan-3A and Spartan-6: After SelectMAP configuration, when Readback CRC is enabled and an ABORT is triggered spurious failures might be flagged in Readback CRC
Design Advisory Alerted on November 19, 2012:
(Xilinx Answer 52716) Design Advisory for Spartan-6 FPGAs - Configuration Readback including SEM_IP or POST_CRC causes power distribution network noise affecting SelectIO and GTP interfaces
Design Advisories Alerted on March 01, 2011:
(Xilinx Answer 40387) Design Advisory for Spartan-6 Configuration - GCLK0 input can glitch at the end of configuration
(Xilinx Answer 40818) Design Advisory for Spartan-6 SelectIO - INTERM_XX not being appropriately turned on in BitGen for Spartan-6 FPGA inputs
Design Advisory Alerted on December 13, 2010:
(Xilinx Answer 39582) Design Advisory for Spartan-6 - When using POST_CONFIG_CRC the INIT_B pin can not be User I/O
Design Advisory Alerted on November 15, 2010:
(Xilinx Answer 38733) Design Advisory for Spartan-6 - LX100/LX100T SMAP x16 max CCLK frequency reduction

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34904 Xilinx Configuration Solution Center N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34904 Xilinx Configuration Solution Center N/A N/A
37249 Xilinx Configuration Solution Center - Configuration Documentation - Older Architectures N/A N/A
AR# 37252
Date 07/31/2017
Status Active
Type Design Advisory
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • More
  • Kintex UltraScale
  • Virtex UltraScale
  • Less