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AR# 37271: 12.2 EDK - ML605 BSB design uses P30_CS_SEL rather than FPGA_FCS_B as CE of BPI Flash
12.2 EDK - ML605 BSB design uses P30_CS_SEL rather than FPGA_FCS_B as CE of BPI Flash
According to the ML605 Board User Guide and Schematic, the P30_CS_SEL (AJ12) signal is used to select between platform flash or BPI flash, and the FPGA_FCS_B signal (Y24) should be used as Chip Enable. However, in the BSB design, the Mem_CEN output from the xps_mch_emc IP is inverted with an util_vector_logic IP, and then the inverted signal is locked to pin AJ12 in UCF. Why is this the case?
The interpretation about the P30_CS_SEL and FPGA_FCS_B is correct. However, the BSB design works too. By default, the unused pinsare tied to ground by BitGen. Since the FPGA_FCS_B pin (Y24) is not used in the BSB design, it is always "0". So, when the BPI Flash is selected by P30_CS_SEL, itis enabled too. The BSB design can also be modified to use FPGA_FCS_B as Chip Enable signal. For example, modify the design as follows:
PORT fpga_0_FLASH_CE_inverter_Res_pin = net_vcc, DIR = O PORT FPGA_FCS_B = net_bsbassign0, DIR = O