AR# 3730


M1.4 CPLD Fitter: Combinatorial logic duplicated with multilevel logic optimization


Keywords: multi, level, logic, optimization, hitop, cominatorial. duplication

Urgency: Standard

General Description:

The CPLD Fitter may duplicate combinatorial logic (2 inpus OR gates) feeding control
signals (CLK, SR, OE, CE) during multi-level optimization increasing
the macrocell count.



IF you run into this situation, you can resolve the issue in
either of two ways.

1. Turn off multi-level logic optimization from the Advanced
optimization tab in the Design Manager, XC9500 template. This
may cause other optimization/fitting problems.

2. Use the KEEP attribute on the 2 inpit OR gates feeding the
control logic. This is a better solution.


A fix is available for this problem in the latest CPLD Tools
update available on the Xilinx Download Area:

These update files also include the changes from previous cpld updates.

All zip files are created using WinZip. To obtain this utility,
access WinZip's web site at

AR# 3730
Date 03/08/2000
Status Archive
Type General Article
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