The following answer records cover current known issues as well as commonly asked questions related to the PlanAhead tool.
NOTE: This answer record is part of the Xilinx PlanAhead Tool Solution Center (Xilinx Answer 37100). The Xilinx PlanAhead Tool Solution Center is available to address all questions related to the PlanAhead tool. Whether you are starting a new design with the PlanAhead tool or troubleshooting a problem, use the PlanAhead Tool Solution Center to guide you to the right information.
(Xilinx Answer 34878) 12.1 PlanAhead - "ERROR: [HD-UCFReader 1] Unrecognized symbol \/leaf_2\/cont_ram\/v16384x72/BU2132"
(Xilinx Answer 35743) 12.1 PlanAhead - Incorrect BIVB DRC errors from PlanAhead
(Xilinx Answer 34793) 12.1 PlanAhead - Synthesis with a netlist as top level in an RTL Project
(Xilinx Answer 34858) 12.1 PlanAhead - Error on constraints when running Implementation in PlanAhead points to merged .ucf
(Xilinx Answer 34876) 12.1 PlanAhead - "RTL I/O Planner view" errors on LOC constraints