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AR# 37412

Virtex-6 FPGA GTH Transceiver - Initialization sequence for ES silicon


This Answer Record discusses the required initialization sequence for the GTH transceiver in ES silicon.


The initialization sequences and code noted below can be generated natively by the Virtex-6 FPGA GTH Wizard v1.6 which is to be officially released with ISE Design Suite 12.4.For an early version of this core, you can use the following ZIP file:

To use this patch, first unzip the files to a location of your choosing, generate an environment variable called MYXILINX and set it to the location of the /rtf directory that is to be generated. For additional information on this variable and how it can be used, see (Xilinx Answer 2493).

The following timing diagrams illustrate the initialization sequence that should be followed after either power up or a GTHRESET has been issued to the transceiver:

An early version of the code thatis generated by the Wizard is available below.Going forward,a patch will be provided that allows the Virtex-6 GTH Transceiver Wizard to generateeither Verilog or VHDLthat implements the required initialization sequences and provides a use modelexample.


Verilog: v6_gthwizard_v1_6_gth_reset.v

VHDL: v6_gthwizard_v1_6_gth_reset.vhd

Linked Answer Records

Associated Answer Records

AR# 37412
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 HXT
  • Virtex-6 FPGA GTH Transceiver Wizard