UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 37424

MIG 7 Series and Virtex-6 DDR2/DDR3 - Using Project Navigator

Description

The standard flow for generating a MIG core is to run the CORE Generator tool standalone (not invoked through Project Navigator). Output files are then generated with the appropriate script files to run either the provided Example Design or User Design through simulation, or generate a bitstream. However, it is possible to implement a MIG core directly through the Project Navigator tool.

What is the recommended flow to generate and instantiate a MIG core within an ISE Project Navigator project?

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you're starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Two recommended flows exist based on whether the user wants to include the Example Design or User Design in the Project Navigator project. The MIG Example Design includes a sample traffic generator that drives the user interface with sample writes, reads, and includes comparison logic to ensure the data written is the data readback. The MIG User Design is ready to be instantiated into a project where the MIG user interface is driven by user logic.

Flow 1 - Running the MIG Example Design in Project Navigator
For users that want to run the MIG Example Design in Project Navigator, the MIG core should still be generated through the CORE Generator tool standalone.
  1. Generate the desired memory interface using the CORE Generator tool standalone.
  2. Navigate to the generated "example_design/par" directory.
  3. Run the provided create_ise.bat (Windows), or create_ise.sh (Linux) script file. This creates an *.ise project file.
  4. Open the *.ise file in Project Navigator. The project will have the Example Design rtl pulled in, all MIG synthesis/implementation options set, and the UCF included.

Flow 2 - Running the MIG User Design in Project Navigator
For users that want to run the MIG User Design in Project Navigator, the Create New Source option in Project Navigator can be used to invoke the CORE Generator interface and open MIG.
  1. Use the "Create New Source" option in Project Navigator to invoke the CORE Generator interface.
  2. Generate the desired MIG core.
  3. The core is added to Project Navigator as a CORE Generator .xco file.
  4. Using the MIG instantiation template file (.vho or .veo), instantiate the core (and include the component declaration for VHDL) in the user's top-level file. The MIG core is now displayed as a submodule of the top-level file.
  5. The UCF constraints that MIG generatesmust be manually added to the user's UCF. Open the generated *.ucf (located in the generated MIG directory under 'user_design/par'). Copy all constraints from this MIG UCF into the user's top-level UCF.
  6. The user design can now be implemented with the MIG core's inclusion.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34283 MIG Solution Center Design Assistant - 7 Series and Virtex-6 FPGA Core Generation N/A N/A
AR# 37424
Date Created 10/05/2010
Last Updated 01/31/2013
Status Active
Type Solution Center
Devices
  • Virtex-6
  • Virtex-7
  • Kintex-7
  • More
IP
  • MIG